Dutch Chip Equipment Maker BESI Loses 14% as Memory Standards Threaten AI Growth Story
Duiven, Friday, 6 March 2026.
JEDEC’s potential adjustment to memory chip height standards could delay adoption of BESI’s hybrid bonding technology by years, undermining the Dutch company’s position in the AI boom.
The Technology at Stake
This story centers on semiconductor packaging technology, a critical component in the modern chip manufacturing process that enables the creation of high-performance processors used in artificial intelligence applications [GPT]. BE Semiconductor Industries, based in Duiven, Netherlands, has positioned itself as a market leader in hybrid bonding technology, which allows chips to be stacked with precision of less than 0.1 to 0.2 micrometers [8]. The company’s stock experienced a dramatic decline on Friday, March 6, 2026, falling by approximately 14% amid concerns about potential changes to industry standards that could delay adoption of this advanced packaging technique [1][3][4].
Understanding Hybrid Bonding Technology
Hybrid bonding represents a significant advancement in semiconductor packaging, enabling thousands of additional connections on a smaller surface area with contact points less than 10 micrometers apart [8]. This technology allows two silicon wafers or chips to be stacked directly, creating more compact and efficient processors essential for AI applications [8]. BESI has collaborated with Applied Materials to develop a complete production line for this technology, specializing in Die-to-Wafer (D2W) hybrid bonding that is crucial for stacking chiplets in complex AI processors [8]. The demand for BESI’s hybrid bonding machines surged in 2025 and early 2026 due to the AI boom, with major manufacturers like TSMC and Intel utilizing the company’s technology [8].
The JEDEC Standards Challenge
The immediate catalyst for BESI’s stock decline stems from potential adjustments by JEDEC, the international standards organization for semiconductors whose members include Samsung Electronics, SK Hynix, Micron, Intel, TSMC, NVIDIA, and AMD [8]. JEDEC is considering increasing the maximum height allowance for High Bandwidth Memory (HBM) chips, which are constructed by stacking multiple DRAM layers like a tower [1]. Currently, chip manufacturers use thermocompression bonding (TCB), an older method, to connect these layers, but the industry was expected to transition to BESI’s more precise hybrid bonding technology [1]. If JEDEC raises the height standard, more DRAM layers could fit within existing specifications without requiring the newer bonding technology, potentially extending the use of TCB and delaying hybrid bonding adoption [1][3][6].
Market Impact and Historical Precedent
The market reaction reflects serious concerns about BESI’s growth trajectory in the AI semiconductor boom. Michael Roeg, analyst at Degroof Petercam, described the development as worrying and noted that JEDEC previously extended height standards approximately two years ago, which reduced pressure on memory manufacturers to transition from TCB to hybrid bonding [1][3][4]. This historical precedent suggests that standards adjustments can significantly delay technology adoption cycles. The analyst takes the current reports “very seriously,” indicating that a similar scenario could push BESI’s expected revenue growth further into the future [1][3]. The stock decline occurred on high trading volumes, with various sources reporting losses ranging from 9.5% to 14% on March 6, 2026 [1][3][4][8]. This represents a significant setback for a company that has been positioned as one of the primary beneficiaries of the global AI boom, particularly as data centers increasingly require advanced HBM chips for AI processing [1].